Four Ways to Create a CAD Workflow: From In-House Design to Custom EDA Tool


An in-house Computer Aided Design (CAD) or Design Services Engineer is responsible for providing efficient, robust and high quality design flow solutions. The day-to-day design flow keeps chip designers and verification engineers productive and focused on their work, preventing them from debugging CAD tools and flows and creating ad hoc, undocumented scripts. Over the lifetime of a project, a high-quality design flow differentiates a company from its competitors and can be the difference between bringing chips to market first or being bottlenecked and unexpected process delays.

And yet, every semiconductor project group faces inefficiencies that prevent them from delivering ideal solutions and limit productivity. CAD engineers today use a patchwork of tools, workflows, and scripts comprised of commercial electronic design automation (EDA) products, commercial or in-house custom add-ons, and in-house intellectual property (IP) , a problem for many project groups due to:

  1. Tool Flow Gaps in Existing EDA Products
  2. The burden of maintaining internal or internally developed tools, flows and scripts
  3. Lack of time to build and test robust and quality internal tools

This inevitably leads to a bunch of problems, as explained in the following sections.

Endless script design loops

The burden of maintaining internal or internally developed tools, flows and scripts is one of the cascading interventions. It might start with a design engineer writing a Perl or Tcl script to overcome an obstacle in the design verification process.

As the project group uses, special cases and functions do not work. The script is reworked to refine it and passed to the chip maintainer for review who notes improved automation and then notices that the script is not handling something critical.

Other problems arise as the project group uses the script. The script is passed to the internal CAD group for ongoing support and maintenance. Other issues arise when the in-house CAD department starts using it. The CAO spends three weeks working on the script to resolve these issues and ongoing maintenance requires one day per week.

It doesn’t take long before supporting and maintaining an in-house script costs between $50,000 and $100,000 a year. Ultimately, the script was necessary for the development process, but the financial and time cost of the project is high and unpredictable.

The maintenance burden is to ensure that existing internal tools and flows continue to function. Other maintenance choirs might add functionality to existing internal tools and streams, and move to a new hardware description language (HDL), such as Verilog to SystemVerilog, or add support for additional HDL due from a third-party IP address. The estimated cost of updating a single internal Perl or Tcl script to support SystemVerilog can be $175,000 and six months of project time.

time is the enemy

The main objective of a company is to bring the silicon device to market quickly. The role of the CAD department is to support designers and verification engineers, which means continuing to support the patchwork of tools, flows and hybrid scripts from commercial EDA products and in-house IP.

Lack of time to build robust tools is a problem. A CAD engineer knows what he wants from a tool, knows how to design, implement and test it, but doesn’t have the time to do it.

Local fixes include:

  • As for open source parser projects, though they never have full language coverage or support for new builds.
  • Rewrite internal flows and scripts and use more robust software engineering methodologies, a difficult task to justify the resources needed to “re-do” the job.
  • Switch from Perl or Tcl to Python for better understandability and functionality. This doesn’t solve the HDL complexity – the SystemVerilog Language Reference Manual (LRM) contains 1,300 pages of complex specifications.
  • Rigging existing commercial EDA tools to do things they weren’t supposed to do often results in unsatisfactory results and reliance on expensive licenses.

At the same time, the project group is taking a huge risk if CAD is unable to consistently deliver best-in-class design and verification flows. Lack of market niches and/or uncompetitive silicon delivery can be fatal to a semiconductor company given new product cycles and high IC development costs.

Solutions exist and range from in-house development of custom tools to purchasing a custom tool built by an EDA company, with variations in between.

Four ways to create best-in-class CAD workflows


Building robust, high-performance CAD tools in-house would yield a proprietary, license-free tool that could be the secret weapon to reliably bring a chip to market first. This would require building a parser from scratch to break free from any licensing agreements.

The disadvantages are:

  • This can take a very long time.
  • This requires a deep understanding of HDL languages ​​and how they are used.
  • The results may not be robust because the underlying infrastructure is weak and untested.
  • The tool may have inadequate testing, leading to an iterative support model.
  • It may not keep up with new developments in HDL languages.
  • Deployment time can be long, ranging from a year to several years.

Of them

License a C++ parser library and hire a software development group to create custom CAD tools that work around current limitations. This solution is an outsourced version of the previous one. Commercially available parsers offer advantages, including full language coverage for VHDL, Verilog, SystemVerilog, and UPF.

Internal CAD groups are often more experienced in scripting style languages ​​such as Perl, Tcl, and Python and may not have deep C++ development expertise. The C++ library can be difficult to use without deep expertise in C++ software development.


Ask an EDA vendor to customize the features/functions needed to enable a design flow. An advantage of this solution would be the support and maintenance of the requested capacity if it is integrated into the main line of the product. A consulting project by the EDA vendor would mean responsibility for ongoing additional consulting services to maintain functionality/function.

Additionally, the company would be beholden to the EDA vendor’s schedule or the vendor might not create or be able to create the customization. The EDA vendor may require upfront payment for non-recoverable engineering costs (NRE) and, if the EDA vendor adds requests to its next release, a feature or custom function becomes available to competitors. Additionally, if the EDA vendor builds a custom tool, there will be ongoing obligations for intellectual property issues and licensing requirements.

Additionally, depending on the nature of the project and engagement, the EDA vendor may provide the requested functionality to their other customers, thereby losing any competitive advantage associated with the features/functions. Many EDA vendors also provide application engineering support to customize the integration of their tool into their customers’ workflows. Since this type of expertise is typically provided to other large licensees, it is unlikely to confer competitive advantage.


License a CAD tools development platform that contains built-in HDL parsers, industrial-grade databases, and support for industry-standard file formats for in-house development using environments common scripts. A platform solution like this is for design, verification, and CAD engineers to quickly build custom applications targeted for semiconductor design and verification.

A robust, high-performance, and easy-to-use CAD tool development platform should:

  • Provide comprehensive analysis of Verilog, SystemVerilog, Verilog-AMS, VHDL, Liberty and UPF.
  • An intuitive API with language familiar to a hardware engineer such as Python that abstracts the complexity and allows for specific control where needed.
  • Be pre-tested on a large set of benchmarks that prove typical use cases and all behaviors of the HDL language, including constructs and use cases.
  • A support model that describes the use of the tool and access to consulting services to complete the development.
  • Examples of fully operational applications easily modified for the specific case of a user.

CAD tool development platform

The biggest challenge facing in-house groups is accessing HDL analytics environments that are robust, easy to use and maintain, and always supported. A CAD tool development platform that offers both ease of use and robust capabilities would free the group from the limitations of commercial EDA workflows while providing capabilities to differentiate its design workflow. Additional benefits are cost savings on EDA tool licenses, time savings on CAD tools, flow and script development, and increased productivity for design, verification, and CAD engineers.

The CAD tool development platform would require an upfront investment, rather than using free scripting tools like Perl and Tcl, a downside that needs to be considered. With the move from Verilog to SystemVerilog, for example, simple Perl or Tcl scripts are not feasible due to the added complexities of the language. A CAD tool development platform designed for HDL exploration and modification will enable innovative new tools and workflows not possible with general purpose text analysis capabilities.

A CAD tool development platform is an investment that makes full use of human capital; valuable R&D resources thinking about building the best ICs, not struggling to debug ad hoc Perl scripts.

Another downside is the question of the robustness of the parsing capability for SystemVerilog, VHDL, or UPF. To be successful, the platform must be based on a widely used and tested HDL analyzer library. Without it, each new design or project will reveal more analyzer limitations. Only parsers actively used by thousands of engineers and actively maintained can handle arbitrary new designs.

By bridging the gaps in a CAD workflow and breaking out of the endless cycle of designing and debugging scripts, a licensed CAD tool development platform provides the ability to leverage commercial-grade HDL analyzers while simplifying their use.

Daniel Hoggar is a senior technical staff member at Verific Design Automation.

Related content

Source link

Comments are closed.